The present invention relates to the use of a photoresist mask in semiconductor device production. More particularly, the present invention relates to etching a dielectric layer through a photoresist mask during the production of a semiconductor device.
During semiconductor wafer processing, features of the semiconductor device are defined in the wafer using well-known patterning and etching processes. In these processes, a photoresist (PR) material may be deposited on the wafer and then is exposed to light filtered by a reticle. The reticle may be a transparent plate that is patterned with exemplary feature geometries that block light from propagating through the reticle.
After passing through the reticle, the light contacts the surface of the photoresist material. The light changes the chemical composition of the photoresist material such that a developer can remove a portion of the photoresist material. In the case of positive photoresist materials, the exposed regions are removed, and in the case of negative photoresist materials, the unexposed regions are removed. Thereafter, the wafer is etched to remove the underlying material from the areas that are no longer protected by the photoresist material, and thereby produce the desired features in the wafer.
To provide increased density, feature size is reduced. This may be achieved by reducing the critical dimension (CD) of the features, which requires improved photoresist resolution. One way of improving photoresist resolution is by providing thinner photoresist masks.
New photoresist materials (193 and 157 nm PR) are being pursued to produce small CD sizes in the photoresist, but these resists are less resistant to damage from the plasma than previous masks of DUV and 248 nm photoresist. Also, with the current single layer approach, increasingly thinner resist must be used to match the resolution of the features. This may not provide enough resist for the dielectric etch and may cause other complications, such as striation, line edge roughness, and line wiggling. In order to keep up with shrinking feature dimensions, the industry has been investigating new technologies such as multi-layer approaches involving several processing steps. The switch to new technologies will undoubtedly be expensive and time-consuming.
In an effort to reduce the coupling capacitance levels in integrated circuits, the semiconductor industry has engaged in research to develop materials having a dielectric constant lower than that of SiO2, which materials are suitable for use in forming the dielectric layers in integrated circuits. A number of promising materials, which are sometimes referred to as “low-k materials”, have been developed. In the specification and claims, low-k materials are defined as materials with a dielectric constant k that is less than 4. Fluorosilicate glass is one example of a low-k dielectric, which has a dielectric constant of about 3.7. This composes an about 7-9% fluorine doped into SiO2.
There are several kinds of low-k materials currently being developed and in use in the semiconductor industry, i.e. fluorinated silicon oxyfluoride (FSG), hydrogen silsesquioxane (HSQ), spin-on organic materials (Dow's SiLK™ is a non-fluorinated, highly aromatic, organic spin-on polymer with a reported k of 2.65), and inorganic systems deposited by chemical vapor deposition (CVD) such as organosilicate glass. By way of example, but not limitation, such organosilicate dielectrics include CORAL™ from Novellus of San Jose, Calif.; Black Diamond™ from Applied Materials of Santa Clara, Calif.; Aurora™ available from ASM International N.V., The Netherlands; Sumika Film® available from Sumitomo Chemical America, Inc., Santa Clara, Calif., and HOSP™ from Allied Signal of Morristown, N.J. Organosilicate glass materials have carbon and hydrogen atoms incorporated into the silicon dioxide lattice which lowers the density, and hence the dielectric constant of the material. A dielectric constant for such films is typically <3.0.